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INDIAN INSTITUTE OF SCIENCE EDUCATION AND RESEARCH (IISER) PUNE
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An Autonomous Institution, Ministry of Human Resource Development, Govt. of India
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Seminars and Colloquia

Physics

Circuit optimization for Cliffort+T library: Paving a way to get higher fidelity and higher values of nonclassicality witnesses in IBM's quantum processors 
 
Thu, Jan 31, 2019,   03:00 PM at Seminar Hall 31, 2nd Floor, Main Building

Dr. Abhishek Shukla
University of Science and Technology of China

Abstract:
Recently, a number of quantum computation and communication tasks have been implemented using IBM's open source quantum computing facility. Due to lower fidelity of gates used in IBM's processors than other experimental architectures, like NMR and nitrogen vacancy centers etc., fidelity of the desired states falls drastically with the size of the circuits and hence affects the final outcome. We have observed that many of the experiments implemented on IBM's processors involve unoptimized circuits. I will present our algorithmic approach of circuit optimization for Clifford+T gate library used in IBM's quantum processors by minimizing gate counts and levels. We have employed this optimization approach and obtained higher value of noclassicality witnesses and states with higher fidelities in comparison to the values obtained in previous experiments, done on IBM's quantum processors. If time permits, I will also describe current approach we are pursuing in order to realize many body spin quantum simulator exploiting nitrogen vacancy color centers in diamonds.  
 

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