By Hemangee Kapoor, Indian Institute of Technology Guwahati

Abstract 

With the rapid growth of Artificial Intelligence and Machine Learning in everyday applications, there is an increasing demand for fast and efficient computation. Hardware accelerators have emerged as a key solution to meet these performance requirements. This talk provides an overview of recent advancements in deep learning accelerators, from general-purpose CPUs to custom hardware designs. We will explore design constraints like memory latency, performance, and energy which influence these architectures. The talk will also delve into selected accelerator designs, including a near-memory accelerator that exploits sparsity and redundancy in data, highlighting how architectural choices can unlock performance under real-world constraints.